The manufacture of an integrated circuit (IC) in a microelectronics device involves the formation of multiple patterned metallization layers successively overlaid and stacked upon one another. Inside these metallization layers, numerous electric wirings typically referred to as the metal lines are formed in the dielectric substrate in the form of horizontal line by methodically implementing a series of fabricating processes, such as a photolithography process, an etch process, a film deposition process, a doping process and so on. Intercommunications among the stacked metallization layers rely on numerous interconnects which are metal fillings, such as aluminum or copper fillings, filled in vias (a.k.a. through-substrate-vias or through-layer-vias) or contacts vertically penetrated through the inter-metal dielectric (IMD) layers or the inter-layer dielectric (ILD) layers in the respective stacked metallization layers, descending to contact and connect with the underlying horizontal metal lines or vias, and usually formed by an etch process.
Owing to a critical concern with a resistive-capacitance (R×C) delay time characteristic dominating the circuit performance in IC, the inter-metal dielectric or inter-layer dielectric is generally made of material has a dielectric constant to be as low as possible, such as an extremely low-k (ELK) material, so as to improve the R×C delay time characteristic and to well insulate the respective metallization parts from each other for preventing crosstalk that degrades device performance by slowing circuit speed.
During a fabrication of the metal lines, the interconnects and the through-substrate-vias, for the sake of forming the vias or contacts accurately, formations of etch stop layers are introduced, as well as in order to prevent the migration of a metal material into an adjacent dielectric layer, formations of diffusion barrier layers are introduced. Accordingly, in the state of the art technique, material having a relatively lower etch rate and dielectric coefficient to gain better R×C delay time characteristic for the wafer is conventionally selected to be made as an etch stop layer, such as material selected from the group consisting of silicon carbide, silicon nitride, SiCN, SiOCN and a combination thereof. Nevertheless, a composite etch stop layer made of a tetraethoxysilane (TEOS) oxide layer overlying the conventional silicon-based etch stop layer is developed to further reduce the overall thickness and the dielectric constant for the etch stop layer.
Moreover, since metal ions, in particular copper ions, have a high tendency to migrate into an adjacent dielectric layer and ordinary oxides can not block copper ions well enough and may easily react with copper to produce undesirable copper oxides that reduce the conductivity of the copper layer, a barrier layer conventionally comprised of nitrogen in the form of a metal nitride or silicon nitride is usually introduced to be formed between an IMD/ILD layer and a copper layer for blocking copper ions.
However, the etch selectivity of the ELK layer with respect to the composite etch stop layer is not yet good enough to be satisfied, which fails to overcome a series of issues of the over etch and non-uniform etch issues resulted form different etch rates varied at center and edge portions or at dense and sparse (iso) portions for a wafer, the yield drop issue resulted from the metal damage issue and the chamber risk issue during the etch process.
Another concern with the composite etch stop layer is that although it performs better R×C delay time characteristic as compared with that of a single silicon-based layer of etch stop layer, the composite etch stop layer sandwiched between layers all over the whole wafer still brings significant affections on the R×C delay time performance for the IC especially for sub-micron semiconductor technology. Moreover, for efficiently obstructing the diffusion attacking from the metal ions, it is desired to find a diffusion barrier layer has the expected capability of well preventing diffusions from metal ions. In addition, such a multiple layered structure also raises an adhesion issue among layers.
There is a need to solve the above deficiencies/issues.